1. Field
This disclosure relates generally to semiconductor devices, and more specifically, to configurations of conductive elements for semiconductor devices.
2. Related Art
As integrated circuits continue to evolve, lithography dimensions continue to decrease. Present day lithography is in the range of 0.028-0.50 micron. As a result, the semiconductor die continues to decrease in size. As a result of the decreased size of the semiconductor die, packaging issues are created that heretofore were non-existent. The decrease in semiconductor die size results in bond posts which are external to the die being removed farther and farther from the die in the semiconductor package, which encapsulates the die. As a result, the wires used to connect bond pads on the semiconductor die to bond posts in the package are becoming increasingly longer. Another issue is the high pin count resulting from increased integration afforded by the miniaturization. As a result of increased pin count, more pads per side of a package have to be included. The addition of pads to a side of an integrated circuit further increases the wire length because more bond posts have to be added farther from the side of the integrated circuit die.
Long wire length is problematic for several reasons. A first reason is the fact that long wire lengths result in many integrity problems such as shorting caused by wire sweep. Wire sweeping occurs when the encapsulant used to encapsulate the die is poured into a cavity and causes the wires to move from their original locations and contact each other. Additional issues with increased wire length include the degradation of electrical performance of the integrated circuit package.